This invention relates to circuits for converting the voltage levels of binary digital logic signals. More particularly, it is concerned with circuitry for converting from voltage levels for transistor-transistor-logic (TTL) to voltage levels compatible with metal-oxide-silicon (MOS) logic.
One widely used well-known family of logic integrated circuits employing bipolar transistors is known as transistor-transistor-logic (TTL). For circuits of this family it is specified that an output voltage of 0.4 volts maximum defines a logic 0 and an output voltage of 2.4 volts minimum defines a logic 1. In order to provide tolerances for inadvertent variations including noise, the maximum input voltage for a logic 0 is 0.8 volts and the minimum input voltage for a logic 1 is 2.0 volts. Another widely used family of logic circuits is known as metal-oxide-silicon (MOS) logic. The circuits of this logic family employ a much wider voltage excursion to represent logic 0 and logic 1. For example, with a 5 volt operating voltage logic 0 is very close to ground and logic 1 is very close to the 5 volt operating potential.
Frequently it is desirable to apply signals at TTL logic levels to MOS logic circuits for further processing. Although MOS logic gates operating with a 5 volt operating potential can be fabricated to provide a tripping point between 0.8 volts and 2.0 volts, the logic 1 level of 2.0 volts is not sufficiently high to drive MOS gates effectively and the logic 0 voltage of 0.8 volts is not sufficiently low to prevent MOS gates from false triggering in the presence of noise. Thus, conversion or interface circuitry is required to convert the TTL logic voltages to appropriate voltage levels for MOS logic circuits. Various conversion circuits have been designed to provide this function and these circuits are satisfactory for many applications. For many situations, however, it is desirable that the conversion circuit be extremely simple employing a minimun number of components and be amenable to fabrication with MOS integrated circuitry. It is also desirable that the circuit operate at high speed, have high immunity to noise, and provide isolation between the stray capacitance due to wiring and the MOS circuitry.